1. Field of the Invention
The present invention relates to a DC current reduction circuit, and more particularly, to a DC current reduction circuit that reduces the DC component from a current output from a current output element such as a photodiode, in which an AC current and a DC current are superimposed.
2. Description of the Related Art
Current that is output from a current output element such as a photodiode includes direct (DC) current and alternating (AC) current. At the same time, for most applications only AC current is required. In such cases, because the DC current degrades the dynamic range of an active circuit connected subsequent to the current output element, it is necessary to reduce the DC current.
With regard to this problem, in the conventional art there is a method that uses a high-pass filter to transmit only the AC component to the subsequent active circuit and a method that uses a low-pass filter to extract the DC component from the original signal and uses the extracted DC component to cancel the DC component of the original signal.
However, the above-described conventional art has the problems described below. That is, almost all the filters used in the conventional art are constructed using fixed resistors and fixed capacitors, and therefore their cutoff frequency is fixed. Consequently, there is a trade-off between tracking ability of a circuit to track abrupt changes in the DC component that occur suddenly and attenuation loss of the AC component to be sent to the subsequent active circuit. In addition, in a case in which the resistors and the capacitors of the filter are formed within an integrated circuit formed on a semiconductor substrate, in terms of chip and package costs there are restrictions on the lower limit of the cutoff frequency, which leads to limitations on applications.
By contrast, in an invention described in Japanese Patent Laid-Open No. 2005-286664, high-resistance channels of MOS transistors operating under subthreshold characteristics (hereinafter MOS resistors) are used as the above-described resistors to achieve an enhancement of the lower limit on the cutoff frequency within a limited chip surface area. In addition, in the event that there is an abrupt displacement in the DC component above a prescribed voltage, the MOS resistors operate linearly and cause the cutoff frequency to increase temporarily, quickly clamping the voltage displacement.
However, in the configuration described in Japanese Patent Laid-Open No. 2005-286664, in a case in which the abruptly displaced voltage of the DC component does not attain the prescribed size, the MOS resistors do not operate linearly and the DC level cannot be clamped quickly. Moreover, the ability to quickly clamp with the linear operation of the MOS resistors is limited to voltages in excess of the prescribed value, such that, with respect to residual DC components below the prescribed displacement, the DC level cannot be clamped quickly.